1. Field of the Invention
The present invention relates to a numerical controller, and in particular, relates to a numerical controller having a fault analysis data acquisition function when an alarm of the numerical controller is raised and a numerical control system in which the numerical controller is connected to a network.
2. Description of the Related Art
In a numerical controller, units such as a CPU, flash memory, motor control LSI, and I/O control LSI are connected to an internal bus thereof directly or via control LSI and read and write data between these units and a fault occurrence notification signal indicating that an alarm is raised in some unit flow through the internal bus.
Conventionally, when an alarm is raised in the internal bus of a numerical controller, a log of a related register or the like has been left in accordance with the alarm. In this case, how to leave appropriate information automatically is important for fault recovery.
In JP 05-108398 A, when the same alarm is raised successively, the amount of information for fault analysis is increased by changing places where a log is kept. When, for example, as illustrated in FIG. 6, an alarm of servo control LSI 6 is raised, a register 7 related to the alarm in the servo control LSI 6 is kept in the log for the first alarm and if the next alarm is the same alarm, another register determined in advance and not illustrated, DRAM 2 or the like is kept in the log.
However, while final values of the memory, registers and the like are kept in the log, no bus cycle such as which CPU or LSI writes to which register and which register is read is kept. In the fault analysis, information of a log alone may be insufficient and it is sometimes necessary to examine what kind of bus cycle arose and in that case, a bus trace circuit that stores bus cycles may be used.
JP 2010-205064 A discloses a bus trace circuit inside LSI and there is a plurality of trace target bus circuits and when a fault occurrence notification signal of each circuit is output, the trace circuit switches the trace target bus to acquire trace data corresponding to each alarm at a time close to the time when a fault occurs without increasing the circuit scale. In the example of FIG. 7, a first bus 17 and a second bus 18 have respective bus control circuits 15 and 16, and when each bus control circuit detects an error and notifies a trace circuit 11 of an error notification signal, a target determinator 12 of the trace circuit 11 determines the bus that has output the error notification signal as a trace target and notifies a target selector 13 of a trace selection signal, and the target selector 13 stores the bus that has output the error notification signal in a buffer memory 14. Though omitted in FIG. 7, other circuits and input/output of LSI are connected to the first bus and the second bus.
For an internal bus connecting LSI, however, in some cases there is a time difference between the cause of an alarm and an occurrence time of the alarm, for example, like a parity error of a memory, the true cause of an alarm is data to be written that is already damaged due to a failure of LSI that generates a write cycle when data is written into the memory, and the alarm is raised by reading the data. In that case, according to JP 2010-205064 A, necessary trace data cannot be acquired. Alternatively, JP 2010-205064 A contains a description of a trace target fixed mode, and when the mode is used, the mode needs to be manually set and trace data cannot be acquired automatically.
Storing all trace data can be considered for fault analysis and in that case, a large quantity of memory as a storage location needs to be prepared, leading to an increased circuit scale. Thus, the address range or the like is frequently set to a bus trace circuit to fetch only bus cycles satisfying the setting.
However, the bus cycle to be fetched is different from alarm to alarm and thus, conventionally, information such as a log left is checked after an alarm is raised and if the cause of the fault is not known from the information, it becomes necessary to consider settings to be made to the bus trace circuit, create software dedicated to make the settings to a setting register of the bus trace circuit, and install the software in a numerical controller, taking time and efforts.